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Build your own MIC1 – IJVM on FPGA 01


It’s the “DSD time” at the Department of Electronic and Telecommunication in University of Moratuwa. Just to give the idea; DSD aka Digital System Design is one of most challenging yet interesting modules which offered to the semester 5 undergraduates of the department. In this module they have to develop some RTLs by themselves and as in groups and deploy them into FPGAs as their Individual and Group Projects. When I was an undergraduate same module was taught us in Semester 7(Old Curriculum) and we studied a lot on Processor Architecture with the basis of IJVM (MIC1,2,3 architectures) and at the final semester we got another exam free module called “Advanced Digital System Laboratory” in which we had to implement a stack based processor as its project.

In this article series I am going to share my experience and thoughts on what we did, how can be done the implementation of your own IJVM on FPGA. We will start this article series by brain storming the following,

  • · What are the components/modules require
  • · What are the data/address bus sizes?
  • · Memory depth?
  • · What are the ALU operations in interest?
  • · What are the instructions?

As for the reference of this implementation, I use PIC16F84 datasheet, concepts of Z80 processor demonstration kit and ‘Structured Computer Organization’ by Tanenbaum. Therefore the design will be inspired by some qualities and properties of PIC16F84 and Z80.

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2014 June 22 Posted by | Electronics, FPGA, MIC1 IJVM, Technology | 2 Comments

   

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