Thilina's Blog

I might be wrong, but…

Build your own MIC1 – IJVM on FPGA 01

It’s the “DSD time” at the Department of Electronic and Telecommunication in University of Moratuwa. Just to give the idea; DSD aka Digital System Design is one of most challenging yet interesting modules which offered to the semester 5 undergraduates of the department. In this module they have to develop some RTLs by themselves and as in groups and deploy them into FPGAs as their Individual and Group Projects. When I was an undergraduate same module was taught us in Semester 7(Old Curriculum) and we studied a lot on Processor Architecture with the basis of IJVM (MIC1,2,3 architectures) and at the final semester we got another exam free module called “Advanced Digital System Laboratory” in which we had to implement a stack based processor as its project.

In this article series I am going to share my experience and thoughts on what we did, how can be done the implementation of your own IJVM on FPGA. We will start this article series by brain storming the following,

  • · What are the components/modules require
  • · What are the data/address bus sizes?
  • · Memory depth?
  • · What are the ALU operations in interest?
  • · What are the instructions?

As for the reference of this implementation, I use PIC16F84 datasheet, concepts of Z80 processor demonstration kit and ‘Structured Computer Organization’ by Tanenbaum. Therefore the design will be inspired by some qualities and properties of PIC16F84 and Z80.

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2014 June 22 Posted by | Electronics, FPGA, MIC1 IJVM, Technology | 2 Comments

Connecting Digilent ATLYS board with Xilinx iMPACT

In my previous article I discussed how to setup MATLAB for hardware co-simulation with Digilent Atlys FPGAs. Since Electronic undergraduates in level 3 and level 4 at University of Moratuwa (where I belong) are rushing through their Digital System Design individual and group projects and most of the use Atlys Spartan 6 FPGA as their development platform, I am going to put this quick post so that can help them with their projects. In this article I am going to share my experience on setting up Xilinx for Detect Digilent USB cable.

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2012 September 27 Posted by | Electronics, FPGA, Technology | , , , , | 1 Comment

Setting up MATLAB with Atlys Spartan 6 FPGA for Hardware Co-simulation

In my previous articles I discussed how to perform a hardware co-simulation using MATLAB, by using Digilent Atlys Spartan 6 FPGA development kit. But many of my colleagues had the problem of setting up MATLAB for Hardware co-simulation. With a help of a friend of mine, we managed to configure MATLAB for hardware co-simulation. In this short article I am going to share my experience on setting up MATLAB for hardware co-simulation with Atlys Spartan 6 Development Kit.

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2012 September 26 Posted by | Electronics, FPGA, MATLAB, Technology | , , , , | 9 Comments

Hardware co-simulations for image processing applications using MATLAB Simulink Xilinx Block-set

When working with image processing applications on hardware level, during the simulations I personally felt, very hard to work with bit/byte data, without seeing the resulting image/video data. For this kind of application we need to stream in and stream out data bits/bytes to and for the hardware module we implemented. MATLAB Simulink with combination of Xilinx Block-set gives great help in dealing this issue. By using MATLAB we can reshape images in to data stream as well as reshape data streams back in to images in MATLAB environment as I discussed in my previous article.

But the problem rises with the complexity of the system in interest. According to the performance of your computer the simulation time can be varying, sometimes it may be able to take hours. Hardware Co simulations on MATLAB come as the solution for the pc performance limitation issue. In this article I am going to share my experiences on performing a hardware co-simulation on MATLAB with the FPGA development kit Atlys Spartan 6 with xls45-3 FPGA.

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2011 December 6 Posted by | Electronics, FPGA, Image Processing, MATLAB, Technology | 1 Comment

View Streamed Image data on Simulink in Real-time

Two more months to go and it ends the final semester of final year at the University. All are rushing to finalise their final year projects, do simulations again and again, create test cases etc. Since our final year project is related to FPGA implementation of an image processing application, we used to work with images and they need to send as a data stream to the FPGA for processing. When performing simulations (Using MATLAB Simulink Xilinx Block set) we created the image in to data stream and sent it via Ethernet cable to the FPGA, so called Hardware co-simulation. The way we created the data stream is described in my previous article and I wish to add another article on Hardware Co-simulations in future.

However we had a small problem which the resulted image can only be viewed after performing the full simulation, which takes a lot of time, sometimes it takes hours. So finally by using a combination of MATLAB function block, unit delay block and video viewer block we were abled to design a model which reshapes the image stream back to its original image in real-time. From this article I will share my experience on creating the real-time image viewer for image streams.

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2011 September 25 Posted by | Electronics, FPGA, Image Processing, MATLAB | 11 Comments

Streaming data from MATLAB-workspace to Simulink

Since we are having our final year project term in the university we are working in a rush with the projects. Our final year project is related to a hardware implementation related to image processing; we use MATLAB together with Xilinx for simulations. This is something I did to make our final year project simulations easy. In this article I share my experience on how to send workspace data to MATLAB simulink with respect to a clock and data enable flag generated by simulink blocks.

MATLAB simulink block “from workspace” allows us to send workspace variables to simulink. The data format must be with at-least two column matrix since the first column is considered as the time stamp. To get a basic idea about how “from workspace” block works, let’s use following simulink model.


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2011 July 1 Posted by | FPGA, Image Processing, MATLAB | 6 Comments

Using Xilinx Core Generator – Division in FPGA

Xilinx ISE comes with a number of cores which can be used with their products. While we are working on our Final Year Project at the university we used a number of these cores to make our work easy. In this article I will share my experiences on Xilinx core generator by implementing a division core as an example.

Verilog HDL supports division by a constant such as

· (constant)/ (constant) or

· (variable)/(constant with power of two manner)

But when it goes to division of variable by variable or constant by variable it will not support a simple division and must use separate core (using Xilinx core generator or an advanced module designed by someone else). Look at following example.

module simpleDivision(
  input clk;
  input [7:0] div;
  output reg [7:0] quo = 0;
  always @ (posedge clk)
    quo = div/4;

I used following test bench program to simulate above code and observed that the results will come within single clock cycle as below.

module test_simpleDiv;
  reg [7:0] div;
  reg clk;
  wire [7:0] quo;
  simpleDivision uut (
  initial begin
    div = 0;
    clk = 0;
    #10 div = 20;
    #10 div = 5;
    #10 div = 121;
    #10 div = 13;
    #30 $finish;
  always #5 clk = ~clk;

Note that the line

always #5 clk = ~clk;

will generate the clock signal with the period of 10ns. Result was as below.


When It goes to (variable/variable) division, Xilinx core generator supports a division core with two modes which can be used with division,

· Radix2 mode

· High Radix mode

I’ll discuss how to generate the radix division core using Xilinx core generator, add a simple wrapper to the core and simulation results of the division.

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2011 June 6 Posted by | Electronics, FPGA, Technology | 8 Comments

Getting started with FPGA – My first design on Xilinx

The module Digital system design is another very interesting module we studied in our Last semester (L4S1). In this module we got a two assignments (individual design and a group project) in-order to get familiar with digital system design with FPGA using verilog HDL. In individual small scale design most of us did some various kinds sequence detectors which can be use as locks, even though it is very small thing for a FPGA designer I thought it will be much better to share my experience which will helps for the beginners to FPGA such as me.

Designing this sequential machine I used my Atlys Spartan 6 FPGA Development kit to implement the design and used Xilinx ISE 12.3 as the design suite. I will share the whole process I did in design of this simple module.

Project Design

You can start a project using Xilinx ISE by fileànew project and the new project wizard window will be appear, the set location, project name, select Top-level source type as HDL and add project description(optional) and click next to continue.


At the next window (project settings window) I selected family as Spartan6, Device asXC6SLX45, package as CSG342C and kept other parameters to be its default values as generated and then clicked next to continue and finally a summary of the project will be display in the wizard and click to finish the project wizard.

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2011 April 22 Posted by | Electronics, FPGA, Technology | 5 Comments


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