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Build your own MIC1 – IJVM on FPGA 01

It’s the “DSD time” at the Department of Electronic and Telecommunication in University of Moratuwa. Just to give the idea; DSD aka Digital System Design is one of most challenging yet interesting modules which offered to the semester 5 undergraduates of the department. In this module they have to develop some RTLs by themselves and as in groups and deploy them into FPGAs as their Individual and Group Projects. When I was an undergraduate same module was taught us in Semester 7(Old Curriculum) and we studied a lot on Processor Architecture with the basis of IJVM (MIC1,2,3 architectures) and at the final semester we got another exam free module called “Advanced Digital System Laboratory” in which we had to implement a stack based processor as its project.

In this article series I am going to share my experience and thoughts on what we did, how can be done the implementation of your own IJVM on FPGA. We will start this article series by brain storming the following,

  • · What are the components/modules require
  • · What are the data/address bus sizes?
  • · Memory depth?
  • · What are the ALU operations in interest?
  • · What are the instructions?

As for the reference of this implementation, I use PIC16F84 datasheet, concepts of Z80 processor demonstration kit and ‘Structured Computer Organization’ by Tanenbaum. Therefore the design will be inspired by some qualities and properties of PIC16F84 and Z80.

So we will look at our big picture of this implementation as follows,


First we will look upon the Data path elements, later ISA and Control. After having the basic idea of each module and the system, we can start implementing each and finally to get them all together to build the IJVM and its wrapper to program and use.

Basic Structure of the data path of an IJVM will be as follows,


There are two main data buses, that is B bus and C bus and there is another data bus called A bus, which connects the accumulator to the ALU.

If we go one level deep into the data path, we can divide it to three major components, that is;

  1. Registers (SFR and GPR)
  2. ALU and Shifter
  3. Memory and I/O

Special Function Registers are required to perform its dedicated task inside the processor.

Register Task
MAR Memory Address Register, this register is connected to the address bus of the system, whenever there is a memory access, (in our case to the data memory), the memory address had to place on this register and perform the read or write action.
MDR Memory Data Register, When there is a memory access, data interchange is done using this register. If it is a memory read, after a specified number of cycles initiating the memory read, data will be (should) available in this register. At the same time, if it is a memory write, data to be written to the memory must place before initiating the memory write command.
PC Program Counter, this register contains the address of next instruction to be executed and it points to the specific instruction at the program memory. Incrementing of the programming counter either can be done via the ALU or by separate hardware depending on your design requirement.
MBR Memory Buffer Register, It stores the data being transferred from immediate access store to the processor. MBR cannot be loaded using C bus but by only memory.
H Hold Register, also known as Accumulator Register in some cases, holds the second input to the ALU, not that this will be hardwired to the ALU, so that there will be no requirement of output enable signal for this register.
SP Stack Pointer, the register holds the address of the Top of Stack Location. In stack based operations this value should be loaded into the MAR and modify the value of it accordingly.
TOS Top of Stack, this register hold the data pointed by the stack pointer in memory.
CPP Constant Pool Pointer, points to the starting address of constant pool
LV Local Variable Pointer, points to the top of local variable frame.
PORTx PORTs are used as I/O registers, in general case each I/O pin will have its own address and the data will be written to them, but for the ease of our design, we set some internal registers which are hardwired to the I/O port of the processor.
TRISx TRISx, This register will define the direction of each I/O pin of each I/O port as in PIC microcontrollers.

We can add some general purpose registers to the design in order to make things easier when we run our programs in the design.

In the case of memory, we require two memory modules that are for program memory and data memory. We can use a single memory and divide it in to two as a ROM and a RAM, or we can use two RAMs which one of them (for the ROM), data writing is prohibited to the Processor, but possible to outside. Now our picture of the Datapath will be as,


Before we proceed, if we look upon an overview of the control and assembly instructions to be implemented,



From this point I conclude my first article on MIC 1 – IJVM on FPGA, from next article I will share how to build the system block by block and interconnect them as the processor. For more information please refer ‘Structured Computer Organization’ by Tanenbaum and the article of IJVM implementation on Reconfigurable Digital Systems Research Group page of Dept of ENTC, UoM. Thank you very much for reading.

2014 June 22 - Posted by | Electronics, FPGA, MIC1 IJVM, Technology


  1. Pretty good !
    Reminds me of My Undergrad Studies.

    Department Should Recommend this As Reference Articles

    Comment by Ashok | 2014 June 30 | Reply

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