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Using Xilinx Core Generator – Division in FPGA

Xilinx ISE comes with a number of cores which can be used with their products. While we are working on our Final Year Project at the university we used a number of these cores to make our work easy. In this article I will share my experiences on Xilinx core generator by implementing a division core as an example.

Verilog HDL supports division by a constant such as

· (constant)/ (constant) or

· (variable)/(constant with power of two manner)

But when it goes to division of variable by variable or constant by variable it will not support a simple division and must use separate core (using Xilinx core generator or an advanced module designed by someone else). Look at following example.

module simpleDivision(
  input clk;
  input [7:0] div;
  output reg [7:0] quo = 0;
  always @ (posedge clk)
    quo = div/4;

I used following test bench program to simulate above code and observed that the results will come within single clock cycle as below.

module test_simpleDiv;
  reg [7:0] div;
  reg clk;
  wire [7:0] quo;
  simpleDivision uut (
  initial begin
    div = 0;
    clk = 0;
    #10 div = 20;
    #10 div = 5;
    #10 div = 121;
    #10 div = 13;
    #30 $finish;
  always #5 clk = ~clk;

Note that the line

always #5 clk = ~clk;

will generate the clock signal with the period of 10ns. Result was as below.


When It goes to (variable/variable) division, Xilinx core generator supports a division core with two modes which can be used with division,

· Radix2 mode

· High Radix mode

I’ll discuss how to generate the radix division core using Xilinx core generator, add a simple wrapper to the core and simulation results of the division.

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2011 June 6 Posted by | Electronics, FPGA, Technology | 8 Comments


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