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Getting started with FPGA – My first design on Xilinx

The module Digital system design is another very interesting module we studied in our Last semester (L4S1). In this module we got a two assignments (individual design and a group project) in-order to get familiar with digital system design with FPGA using verilog HDL. In individual small scale design most of us did some various kinds sequence detectors which can be use as locks, even though it is very small thing for a FPGA designer I thought it will be much better to share my experience which will helps for the beginners to FPGA such as me.

Designing this sequential machine I used my Atlys Spartan 6 FPGA Development kit to implement the design and used Xilinx ISE 12.3 as the design suite. I will share the whole process I did in design of this simple module.

Project Design

You can start a project using Xilinx ISE by fileànew project and the new project wizard window will be appear, the set location, project name, select Top-level source type as HDL and add project description(optional) and click next to continue.


At the next window (project settings window) I selected family as Spartan6, Device asXC6SLX45, package as CSG342C and kept other parameters to be its default values as generated and then clicked next to continue and finally a summary of the project will be display in the wizard and click to finish the project wizard.


Adding Code

Now the project is ready to add codes, to add new files right click on un-assigned library files icon on design tab on ISE and click new source.


And on select verilog module as the source type in the wizard window set a file name and click next to continue. At the next window you can set the input, output or inout pins or buses for the module and click next and finish end the wizard.


My first program was a sequence detector; which detects the input sequence key press event {[1] [1] [3] [1]} which has the bit pattern {0010,0010,1000,0010}.Iin this program I got 4 bit wide data input which sends input pattern, one input to reset the system, 4-bit output to indicate last pressed key, 2-bit input to indicate the present state of the state machine and 1-bit output to indicate the unlock/ sequence detected signal. Since I needed to keep the output values remain till next state occur I used outputs as registers and another internal registers to synchronise all operations.

And as the initial conditions as state 0, no key pressed and output to be low or high impedance. The initialization of the module is as below.

module seqDet(
    input           [3:0]    keys;
    input                    reset;
    output    reg            unlock;
    output    reg   [3:0]    keyP;
    output    reg   [1:0]    state;
    reg                      ck;
    initial state = 0;
    initial ck = 0;
    initial keyP = 0;

The next stage is adding the code, in the design stage I needed to activate my system on positive edge of the key press event, but it is not possible to implement code to detect 4 edge detections in single always block, so what I did was take those inputs to a bus (keys[3:0]) and for a change of value of the bus checked whether its greater than zero (if pressed it will be greater than zero), and if so I generated an internal signal to indicate the event using the positive edge detection of it.

always@(keys or reset) begin
    if(keys>0 | reset>0)    ck = 1;
    else                    ck = 0;
always@(posedge ck) begin /* code */

When implementing the sequence machine it was driven by using a set of if else conditions, the full code is as below.

module seqDet(
    input         [3:0]     keys;  //pattern input
    input                   reset; //reset
    output reg              unlock; //unlock flag
    output reg     [3:0]    keyP; //last pressed key
    output reg     [1:0]    state; //current state
    reg                     ck; //internal synchronisation
    initial state = 0;
    initial ck    = 0;
    initial keyP  = 0;
    /* Unlock pattern
    keys 0 1 2 3
    [1] [1] [3] [2] */
    always@(keys or reset) begin
        if(keys>0 | reset>0)     ck = 1;
        else                     ck = 0;
    always@(posedge ck) begin
        keyP = keys;
        if(state==0 & keys[1]==1)begin
            unlock = 0;
            state = 1;           end
        else if(state==1 & keys[1]==1)begin
            unlock = 0;
            state = 2;           end
        else if(state==2 & keys[3]==1)begin
            unlock = 0;
            state = 3;           end
        else if(state==3 & keys[1]==1)begin
            unlock = 1;
            state = 0;           end
        else begin
            unlock = 0;
            state = 0; end

Code simulation

Code simulations can be done using the ISE built in simulator called Isim simulator and writing a test bench file. Adding the test bench file is as same as adding a source file to the project, but only you have to select the source type as verilog test fixture. It is must better to use the test bench file name with the convention t_<unit under test>, for example ‘t_seqDet.v’ in this case.

Next you can add the state conditions you need to make, #<number> (such as #15) will make the delays which you need to use during the simulations, but remember that these #delays are only works with the simulations. My test bench code is as below.

module test_seqDet;
    // Inputs
    reg    [3:0]    keys;
    reg             reset;
    // Outputs
    wire            unlock;
    wire   [3:0]    keyP;
    wire   [1:0]    state;
// Instantiate the Unit Under Test (UUT)
    seqDet uut (
    initial begin
       // Initialize Inputs
          keys = 0;
          reset = 0;
       // Add stimulus here
          #10 keys = 4'b0010; //1
          #10 keys = 0;
          #10 keys = 4'b0010; //1
          #10 keys = 0;
          #10 keys = 4'b1000; //3
          #10 keys = 0;
          #10 keys = 4'b0010; //1
          #10 keys = 0;
          #20 reset=1;
          #30 $finish;

After adding the code, select simulation from the design tab and click on your test bench file. Now expand the ISim simulator on the process window and double click on Simulate Behavioural Model icon or right click on it and click run.


Simulations will be run on ISIM simulator and will display as follows.


Synthesizing and Implement on FPGA

Now again click on the Implementation on the Design tab, the on your top module and double click on Synthesize XST. After design completing this step, you are ready to assign pins of the FPGA development KIT to your design. Now expand the User Constraints and double click on I/O Pin Planning (Plan ahead) Pre Synthesis and it will open the user window to assign pins.

On the Plan Ahead window select I/O ports tab, and assign I/O pins to the ‘site’ column as below. After assigning all pins click save and close.


Now it is ready to download to the FPGA. Now connect the FPGA to the computer and power it on. For first time use will be installed to your computer within few seconds. For the Altera board which I used at the university has a specific procedure to install and for the Digilent Atlys Spartan6 board I used the digilent plug-in to connect the FPGA via Xilinx ISE. After the installation, double click on configure target device icon. Now the ISE will implement the design and runs Xilinx iMPACT to download your program to FPGA. This process consumes some time to complete.


Now in iMPACT window double click on boundary scan icon.


Then go to output menu and click cable setup;


Now check the cable plug-in chck box and click ok to continue. Then right click on the window and select initialize the JTAG chain.


Then add your configuration file (file with *.bit extension) to the download to FPGA and click ok. Finally right click on FPGA icon and click program to start program the FPGA.


You can also generate the RTL schematics, technology schematics using the ISE as follows.



Thank you very much for reading.

2011 April 22 - Posted by | Electronics, FPGA, Technology


  1. Very nice, although I like VHDL instead.

    Comment by Ali | 2011 August 18 | Reply

    • Thank you very much ..

      Comment by Thilina S. | 2011 August 18 | Reply

  2. Thank you, this is very useful for me😉

    Comment by Michele Paolino | 2011 November 11 | Reply

  3. thanks ayya… really helpful

    Comment by Charitha Saumya | 2013 July 30 | Reply

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