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Getting started with FPGA – My first design on Xilinx


The module Digital system design is another very interesting module we studied in our Last semester (L4S1). In this module we got a two assignments (individual design and a group project) in-order to get familiar with digital system design with FPGA using verilog HDL. In individual small scale design most of us did some various kinds sequence detectors which can be use as locks, even though it is very small thing for a FPGA designer I thought it will be much better to share my experience which will helps for the beginners to FPGA such as me.

Designing this sequential machine I used my Atlys Spartan 6 FPGA Development kit to implement the design and used Xilinx ISE 12.3 as the design suite. I will share the whole process I did in design of this simple module.

Project Design

You can start a project using Xilinx ISE by fileànew project and the new project wizard window will be appear, the set location, project name, select Top-level source type as HDL and add project description(optional) and click next to continue.

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At the next window (project settings window) I selected family as Spartan6, Device asXC6SLX45, package as CSG342C and kept other parameters to be its default values as generated and then clicked next to continue and finally a summary of the project will be display in the wizard and click to finish the project wizard.

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2011 April 22 Posted by | Electronics, FPGA, Technology | 5 Comments

   

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